1. Field of the Invention
The present invention relates to a ferroelectric memory device including a ferroelectric capacitor and a method of manufacturing the device.
2. Description of the Related Art
In recent years, a ferroelectric random access memory (FeRAM) using a ferroelectric capacitor has attracted attention a nonvolatile semiconductor memory. For the FeRAM, a 1Tr+1C type has heretofore been proposed in which one cell is constituted of one transistor (Tr) and one ferroelectric capacitor (C).
FIGS. 69 to 72 show a schematic cell structure of the FeRAM of 1Tr+1C type according to related art. As shown in FIGS. 69 to 72, a gate electrode 112 is formed on a semiconductor substrate 111, and a pair of source/drain diffusion layers 113a, 113b are formed on opposite sides of this gate electrode 112 to form a transistor 114. An interlayer insulating film 115 is formed on the transistor 114, and contacts 116a, 116b connected to the source/drain diffusion layers 113a, 113b are formed in the interlayer insulating film 115. Moreover, a ferroelectric capacitor 120 constituted of a lower electrode 117, ferroelectric film 118, and upper electrode 119 is connected to one contact 116b, and a plate line 122 is formed on the upper electrode 119 via a contact 121. A bit line 125 is connected to the other contact 116a via a wiring 123 and contact 124.
Here, the cell of FIG. 70 includes a two-dimensional capacitor in which the lower electrode 117, ferroelectric film 118, and upper electrode 119 constituting the ferroelectric capacitor 120 extend only in XY-directions in a planar manner, and only a plane which is horizontal with respect to a semiconductor substrate plane is used as a capacitor plane. The cells of FIGS. 71 and 72 include a three-dimensional capacitor in which at least one of the lower electrode 117, ferroelectric film 118, and upper electrode 119 constituting the ferroelectric capacitor 120 extend in XYZ-directions in a solid manner. Not only the plane which is horizontal with respect to the semiconductor substrate plane but also a side-surface part of the lower electrode 117 which is not horizontal with respect to the semiconductor substrate plane is used as the capacitor planes.
In the above-described conventional cell structure, the ferroelectric capacitor 120, the plate line 122, the contact 116b connecting the ferroelectric capacitor 120 to the transistor 114, the contact 121 connecting the ferroelectric capacitor 120 to the plate line 122, the wiring 123 and contacts 116a, 124 connecting the bit line 125 to the transistor 114, and the like exist between the bit line 125 and the semiconductor substrate 111. Therefore, since the film thickness of the interlayer insulating film 115 between the bit line 125 and the semiconductor substrate 111 increases, the contact connecting the bit line 125 to the semiconductor substrate 111 becomes very deep. In particular, since the diameter of the contact is increasingly reduced to about 0.15 to 0.18 μm, and the aspect ratio of the contact increases by miniaturization of the memory, it is predicted that it becomes further difficult to form a satisfactory contact with a held size.